An interrupt is an important channel of communication between a data processor and its associated external devices. In many data processing systems, the data input and output is achieved through interrupts. In a real time and embedded system, there is a critical need for very fast response times to incoming interrupts. In industrial applications such as aviation, automation control, and biomedical monitoring systems, the central processing unit (CPU) must have a very fast response time control mechanism, in order to process any type of emergency interrupt in a timely fashion, so as to avoid tragic consequences.
For example, in the general prior art, the pipelined data processor can be divided into five stages:
1) instruction fetch (IF), PA1 2) instruction decode and operand fetch (DI), PA1 3) instruction execution (EX), PA1 4) memory access (MA) PA1 5) write back (WB). PA1 otherwise, storing a first return address of a first interrupt or exception at the first part of the working space, PA1 b) fetching a service routine starting address of the first interrupt/exception and executing a first instruction of the service routine at the starting address, PA1 c) completing the execution of the first interrupt/exception service routine, and PA1 d) returning to either the target address of the branch instruction or the first interrupt/exception starting address, whichever address having been previously stored in the first part of the working space. PA1 a) storing the fetched first interrupt/exception service routine starting address in temporary storage in the pipelined processor, PA1 b) if a second interrupt/exception occurs with a higher priority than the first interrupt/exception, and the first instruction of the first interrupt/exception service routine has not reached the instruction boundary, fetching the first instruction of the first interrupt/exception service routine from temporary storage and storing it in a second part of the working space, or PA1 c) when the first instruction of the first interrupt/exception service routine has reached the instruction boundary, storing the return address of the second interrupt/exception service routine at the second part of the working space, PA1 d) fetching a starting address of the second interrupt/exception service routine and executing the second interrupt/exception service routine, and PA1 e) returning to either the first interrupt/exception starting address or the second interrupt/exception starting address, whichever address having been previously stored in the second part of the working space, after completing execution of the second interrupt/exception service routine.
The pipelined data processor usually has to meet the requirement of "precise interrupt" in processing interrupt requests. That is, when there is an interrupt, the save state and the state of normal execution of the processor must be the same. To meet this requirement, a prior art processor will process an interrupt only at the boundary of an instruction, so that the instruction is either completely executed, or not executed at all. To simplify this type of processor design, those exceptions which are generated by memory access (stage 4) are not processed, so that the time for processing interrupt requests is after the execution stage (stage 3), and before the write back stage (stage 5). Nevertheless, it is also possible to process interrupt requests at different stages, depending on the designer's choice and the processor type.
The pipeline stages of a typical prior art processor are discussed herein to show the disadvantages of this kind of interrupt processing design. The instruction fetch (stage 1) is assumed to require one clock cycle. Also, the method of processing interrupts is assumed to be similar to that of the trap type exception, which requires that the trap instruction be retired before the processor state is stored. Or, if the method of processing interrupts is assumed to be similar to that of the fault type exception, where the fault instruction is discarded before the processor state is stored, there will be further disadvantages, as discussed below.
FIG. 1 shows a program fragment sample, and FIG. 2 depicts the timing relationship of the program fragment sample during a pipelined execution. If I.sub.1 in FIGS. 1 and 2 is assumed to be a branch instruction, the processor will know whether or not a branch is taken, immediately after the stage of instruction execution (T.sub.4). If a branch is taken, the processor will clear the pipeline after the instruction execution stage, and start to execute the branch instruction with the branch target address (T.sub.5) However, if an interrupt occurs between T.sub.4 and T.sub.7, the processor must wait until T.sub.8 to process the interrupt, since that is the time when the target address instruction (D.sub.1) of the branch instruction (I.sub.1) reaches the memory access (MA) stage.
In addition to this undesirable delay, there is yet another disadvantage to the design selection stated above. This is illustrated in FIG. 3, which shows an example of delayed response and processing time, as caused by a second interrupt that occurs after the first interrupt or exception. As shown in FIG. 3, ISR1.sub.i represents the i.sup.th instruction of the interrupt service routine for the first interrupt (or exception), while ISR2i represents the i.sup.th instruction of the interrupt service routine for the second interrupt. If an interrupt or exception occurs at instruction I.sub.1 during the time T.sub.1, the processor will save the processor state 1 (such as program counter, register, and memory content) in the memory access (MA) stage, at T.sub.2 in FIG. 3. At the same time, the processor will fetch the starting address of the interrupt service routine (ISR1.sub.1) from an external memory unit, and send it to Instruction Fetch, to be executed anew by the interrupt service routine, at T.sub.3. If a second interrupt occurs between T.sub.2 and T.sub.5, the processor must wait until the ISR.sub.1, reaches the memory access (MA) stage at T.sub.6 before it can process the interrupt.
Thus, if an interrupt occurs when an instruction in the MA stage is a branch instruction, or when an interrupt occurs at the time the processor is processing another interrupt or exception, no interrupt will be accepted until the branch address instruction or the first instruction of the interrupt service routine reaches the memory access stage. If the processor does not have a cache, or there is a cache miss, the time will be prolonged for fetching either the branch target address instruction or the first instruction of the interrupt service routine. Thus, the time that the processor takes to process an interrupt would be increased. As such, the processor could not satisfy a requirement for real time control.
It is therefore an object of the present invention to improve the interrupt response time performance of a pipelined data processor by overcoming the disadvantages of the prior art.